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rebased two asap7 designs
Signed-off-by: Cho Moon <cmoon@precisioninno.com>
2 parents ec52323 + 37d5718 commit ffab31f

105 files changed

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‎docs/user/FlowVariables.md‎

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| <a name="ADDITIONAL_GDS"></a>ADDITIONAL_GDS| Hardened macro GDS files listed here.| |
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| <a name="ADDITIONAL_LEFS"></a>ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| |
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| <a name="ADDITIONAL_LIBS"></a>ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| |
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| <a name="ASAP7_USE_VT"></a>ASAP7_USE_VT| A space separated list of VT options to use with the ASAP7 standard cell library: RVT, LVT, SLVT.| RVT|
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| <a name="BALANCE_ROWS"></a>BALANCE_ROWS| Balance rows during placement.| 0|
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| <a name="BLOCKS"></a>BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| |
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| <a name="BUFFER_PORTS_ARGS"></a>BUFFER_PORTS_ARGS| Specify arguments to the buffer_ports call during placement. Only used if DONT_BUFFER_PORTS=0.| |
@@ -127,6 +128,7 @@ configuration file.
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| <a name="DETAILED_METRICS"></a>DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0|
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| <a name="DETAILED_ROUTE_ARGS"></a>DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| |
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| <a name="DETAILED_ROUTE_END_ITERATION"></a>DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64|
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| <a name="DETAIL_PLACEMENT_ARGS"></a>DETAIL_PLACEMENT_ARGS| Specify arguments to the detailed_placement call during placement.| |
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| <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| |
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| <a name="DFF_MAP_FILE"></a>DFF_MAP_FILE| Optional mapping file supplied to Yosys to map D flip-flops| |
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| <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
@@ -161,7 +163,7 @@ configuration file.
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| <a name="KLAYOUT_TECH_FILE"></a>KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| |
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| <a name="LATCH_MAP_FILE"></a>LATCH_MAP_FILE| Optional mapping file supplied to Yosys to map latches| |
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| <a name="LAYER_PARASITICS_FILE"></a>LAYER_PARASITICS_FILE| Path to per layer parasitics file. Defaults to $(PLATFORM_DIR)/setRC.tcl.| |
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| <a name="LEC_CHECK"></a>LEC_CHECK| Perform a formal equivalence check between before and after netlists.| 1|
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| <a name="LEC_CHECK"></a>LEC_CHECK| Perform a formal equivalence check between before and after netlists. If this fails, report an issue to OpenROAD.| 0|
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| <a name="LIB_FILES"></a>LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| |
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| <a name="MACRO_BLOCKAGE_HALO"></a>MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| |
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| <a name="MACRO_EXTENSION"></a>MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| |
@@ -388,6 +390,7 @@ configuration file.
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- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
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- [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)
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- [CLUSTER_FLOPS](#CLUSTER_FLOPS)
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- [DETAIL_PLACEMENT_ARGS](#DETAIL_PLACEMENT_ARGS)
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- [DONT_BUFFER_PORTS](#DONT_BUFFER_PORTS)
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- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO)
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- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
@@ -496,6 +499,7 @@ configuration file.
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## All stages variables
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- [ASAP7_USE_VT](#ASAP7_USE_VT)
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- [KEEP_VARS](#KEEP_VARS)
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- [NUM_CORES](#NUM_CORES)
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- [OPENROAD_HIERARCHICAL](#OPENROAD_HIERARCHICAL)

‎flow/.gitignore‎

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settings.mk
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vars.sh
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vars.gdb
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vars.tcl

‎flow/Makefile‎

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# settings.mk is not under source control. Put variables into this
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# file to avoid having to adding the to the make command line.
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# Put variables into this file to avoid having to adding
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# the to the make command line.
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#
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# Out of ORFS trees can have their own settings.mk.
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-include settings.mk
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# ==============================================================================
@@ -389,6 +391,8 @@ endef
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# Custom target to go from synthesis to placement in a single OpenROAD run
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$(eval $(call do-step,1_3_floorplan_to_place, $(RESULTS_DIR)/1_synth.odb $(RESULTS_DIR)/1_synth.sdc,floorplan_to_place))
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$(eval $(call OPEN_GUI_SHORTCUT,yosys,1_2_yosys.v))
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.PHONY: floorplan_to_place
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floorplan_to_place: $(RESULTS_DIR)/1_synth.odb $(RESULTS_DIR)/1_synth.sdc
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$(UNSET_AND_MAKE) do-1_3_floorplan_to_place
@@ -777,6 +781,7 @@ $(eval $(call OPEN_GUI_SHORTCUT,final,6_final.odb))
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$(foreach file,$(RESULTS_DEF),$(eval $(call OPEN_GUI,$(file),DEF_FILE)))
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$(foreach file,$(RESULTS_ODB),$(eval $(call OPEN_GUI,$(file),ODB_FILE)))
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$(foreach file,$(RESULTS_V),$(eval $(call OPEN_GUI,$(file),V_FILE)))
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# Write a def for the corresponding odb
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$(foreach file,$(RESULTS_ODB),$(file).def): %.def:

‎flow/designs/asap7/aes-block/config.mk‎

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export ABC_AREA = 1
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export CORE_UTILIZATION = 40
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export CORE_UTILIZATION = 47
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export PLACE_DENSITY = 0.53
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export BLOCKS ?= aes_rcon aes_sbox
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export SYNTH_HIERARCHICAL = 1
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export MACRO_PLACE_HALO ?= 3 3
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export ROUTING_LAYER_ADJUSTMENT = 0.3
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export HOLD_SLACK_MARGIN = -30

‎flow/designs/asap7/aes-block/rules-base.json‎

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{
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"synth__design__instance__area__stdcell": {
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"value": 2010.0,
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"value": 2090.0,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 7161,
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"value": 7178,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 9936,
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"value": 9788,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 864,
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"value": 851,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 1213,
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"value": 1813,
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},
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"cts__timing__setup__ws": {
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"value": -176.0,
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},
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"cts__timing__setup__tns": {
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"value": -16700.0,
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"cts__timing__hold__ws": {
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},
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"cts__timing__hold__tns": {
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"value": -90.0,
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"value": -6260.0,
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},
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"globalroute__antenna_diodes_count": {
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},
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"globalroute__timing__setup__ws": {
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"value": -150.0,
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},
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"globalroute__timing__setup__tns": {
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"value": -14800.0,
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},
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"globalroute__timing__hold__ws": {
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -152.0,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -12200.0,
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"compare": ">="
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"finish__design__instance__area": {
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"value": 7299,
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"value": 7332,
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}
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}

‎flow/designs/asap7/aes-mbff/rules-base.json‎

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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -2470.0,
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"value": -2370.0,
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"compare": ">="
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},
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -42.3,
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"value": -41.6,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -986.0,
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"value": -857.0,
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‎flow/designs/asap7/aes/rules-base.json‎

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"compare": ">="
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},
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"cts__timing__setup__tns": {
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"value": -1250.0,
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"value": -1100.0,
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},
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -2170.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
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"compare": "<="
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},
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"value": -42.2,
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"value": -825.0,
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‎flow/designs/asap7/ethmac/config.mk‎

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export HOLD_SLACK_MARGIN = -10

‎flow/designs/asap7/ethmac/rules-base.json‎

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"value": -114.0,
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"value": -1710.0,
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"value": -128.0,
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"value": -2160.0,
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"detailedroute__route__wirelength": {
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"value": 243645,
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"value": -1800.0,
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‎flow/designs/asap7/ethmac_lvt/rules-base.json‎

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"value": -907.0,
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"value": -1130.0,
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"globalroute__timing__hold__ws": {

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