Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenROAD-flow-scripts into secure-fix-issue-5988

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

flow/designs/gf12/ariane/config.mk

@@ -37,3 +37,5 @@ export REMOVE_ABC_BUFFERS = 1
 
 export SWAP_ARITH_OPERATORS = 1
 export OPENROAD_HIERARCHICAL = 1
+
+export LEC_CHECK = 0

flow/designs/gf12/tinyRocket/config.mk

@@ -41,3 +41,5 @@ endif
 
 export SWAP_ARITH_OPERATORS = 1
 export OPENROAD_HIERARCHICAL = 1
+
+export LEC_CHECK = 0

flow/designs/rapidus2hp/cva6/rules-base.json

@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -317.0,
+        "value": -287.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -526.0,
+        "value": -680.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -68,7 +68,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -526.0,
+        "value": -680.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

flow/designs/src/bp_quad/bsg_chip_block.sv2v.v

@@ -241513,7 +241513,8 @@ module bsg_mem_1rw_sync_width_p48_els_p256
     .wd_in(data_i),
     .rd_out(data_o),
     .ce_in(_0_net_),
-    .we_in(_1_net_)
+    .we_in(_1_net_),
+    .w_mask_in(48'b0)
   );
 
   assign _1_net_ = ~w_i;

flow/scripts/load.tcl

@@ -3,10 +3,6 @@ source $::env(SCRIPTS_DIR)/util.tcl
 source $::env(SCRIPTS_DIR)/report_metrics.tcl
 
 proc load_design { design_file sdc_file } {
-  # Workaround for flaky STA under mutlithreading starting
-  # with the rel_3.0 upgrade
-  sta::set_thread_count 1
-
   # Do not reload if design is already loaded
   set db [ord::get_db]
   if { [$db getChip] != "NULL" && [[$db getChip] getBlock] != "NULL" } {

flow/util/genElapsedTime.py

@@ -43,7 +43,7 @@ def print_log_dir_times(logdir, args):
 
     # Loop on all log files in the directory
     for f in sorted(pathlib.Path(logdir).glob("**/*.log")):
-        if "eqy_output" in str(f):
+        if any(x in str(f) for x in ["eqy_output", "rsz_lec_check"]):
             continue
         # Extract Elapsed Time line from log file
         stem = os.path.splitext(os.path.basename(str(f)))[0]