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designs: Add ihp-sg13cmos5l Examples
Add all ihp-sg13g2 examples for the CMOS5L PDK and modify all required parts. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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‎flow/designs/ihp-sg13cmos5l/aes/autotuner.json‎

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{
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"_SDC_FILE_PATH": "constraint.sdc",
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"_SDC_CLK_PERIOD": {
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"type": "float",
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"minmax": [
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4.0,
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6.0
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],
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"step": 0
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},
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"CORE_UTILIZATION": {
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"type": "int",
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"minmax": [
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20,
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50
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],
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"step": 1
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},
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"CORE_ASPECT_RATIO": {
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"type": "float",
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"minmax": [
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0.5,
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2.0
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],
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"step": 0
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},
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"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
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"type": "int",
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"minmax": [
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0,
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3
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],
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"step": 1
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},
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"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
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"type": "int",
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"minmax": [
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0,
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3
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],
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"step": 1
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},
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"_FR_LAYER_ADJUST": {
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"type": "float",
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"minmax": [
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0.1,
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0.3
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],
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"step": 0
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},
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"PLACE_DENSITY_LB_ADDON": {
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"type": "float",
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"minmax": [
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0.0,
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0.2
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],
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"step": 0
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},
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"_PINS_DISTANCE": {
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"type": "int",
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"minmax": [
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1,
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4
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],
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"step": 1
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},
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"CTS_CLUSTER_SIZE": {
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"type": "int",
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"minmax": [
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10,
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200
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],
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"step": 1
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},
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"CTS_CLUSTER_DIAMETER": {
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"type": "int",
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"minmax": [
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20,
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400
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],
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"step": 1
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},
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"_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl"
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}

‎flow/designs/ihp-sg13cmos5l/aes/config.mk‎

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export DESIGN_NICKNAME = aes
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export DESIGN_NAME = aes_cipher_top
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export PLATFORM = ihp-sg13cmos5l
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export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export CORE_UTILIZATION = 20
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export CORE_ASPECT_RATIO = 1
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export PLACE_DENSITY = 0.65
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export TNS_END_PERCENT = 100
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export USE_FILL = 1
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export REMOVE_ABC_BUFFERS = 1

‎flow/designs/ihp-sg13cmos5l/aes/constraint.sdc‎

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current_design aes_cipher_top
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set clk_name clk
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set clk_port_name clk
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set clk_period 4.5
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [all_inputs -no_clocks]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/ihp-sg13cmos5l/aes/rules-base.json‎

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{
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"synth__design__instance__area__stdcell": {
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"value": 214000.0,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 200905,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 18614,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 1128,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 1128,
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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -0.225,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
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"value": -0.9,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
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"value": -0.225,
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"compare": ">="
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},
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"cts__timing__hold__tns": {
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"value": -0.9,
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"compare": ">="
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},
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"globalroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
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"value": -0.225,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -0.9,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
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"value": -0.225,
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"compare": ">="
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},
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"globalroute__timing__hold__tns": {
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"value": -0.9,
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 782983,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna__violating__nets": {
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"value": 1,
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -0.225,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -0.9,
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"compare": ">="
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},
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"finish__timing__hold__ws": {
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"value": -0.225,
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"compare": ">="
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},
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"finish__timing__hold__tns": {
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"value": -0.9,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 204761,
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"compare": "<="
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}
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}

‎flow/designs/ihp-sg13cmos5l/gcd/autotuner.json‎

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{
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"_SDC_FILE_PATH": "constraint.sdc",
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"_SDC_CLK_PERIOD": {
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"type": "float",
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"minmax": [
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2.0,
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12.0
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],
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"step": 0
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},
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"CORE_UTILIZATION": {
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"type": "int",
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"minmax": [
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15,
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50
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],
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"step": 1
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},
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"CORE_ASPECT_RATIO": {
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"type": "float",
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"minmax": [
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0.5,
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2.0
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],
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"step": 0
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},
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"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
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"type": "int",
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"minmax": [
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0,
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3
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],
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"step": 1
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},
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"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
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"type": "int",
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"minmax": [
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0,
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3
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],
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"step": 1
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},
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"_FR_LAYER_ADJUST": {
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"type": "float",
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"minmax": [
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0.1,
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0.3
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],
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"step": 0
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},
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"PLACE_DENSITY_LB_ADDON": {
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"type": "float",
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"minmax": [
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0.0,
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0.2
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],
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"step": 0
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},
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"_PINS_DISTANCE": {
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"type": "int",
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"minmax": [
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1,
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3
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],
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"step": 1
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},
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"CTS_CLUSTER_SIZE": {
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"type": "int",
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"minmax": [
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10,
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200
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],
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"step": 1
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},
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"CTS_CLUSTER_DIAMETER": {
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"type": "int",
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"minmax": [
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20,
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400
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],
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"step": 1
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},
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"_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl"
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}

‎flow/designs/ihp-sg13cmos5l/gcd/config.mk‎

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export DESIGN_NAME = gcd
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export PLATFORM = ihp-sg13cmos5l
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export USE_FILL = 1
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export PLACE_DENSITY ?= 0.88
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export CORE_UTILIZATION = 20
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export TNS_END_PERCENT = 100
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export SWAP_ARITH_OPERATORS = 1
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export OPENROAD_HIERARCHICAL = 1

‎flow/designs/ihp-sg13cmos5l/gcd/constraint.sdc‎

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current_design gcd
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set clk_name core_clock
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set clk_port_name clk
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set clk_period 2.8
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [all_inputs -no_clocks]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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