Merge pull request #3975 from The-OpenROAD-Project-staging/synth-oyvind-blackboxes

Make slang ignore Verilog definitions of macros

Author: maliberty

flow/designs/asap7/aes-block/rules-base.json

@@ -99,4 +99,4 @@
         "value": 7206,
         "compare": "<="
     }
-}
+}

flow/designs/nangate45/ariane133/rules-base.json

@@ -99,4 +99,4 @@
         "value": 840911,
         "compare": "<="
     }
-}
+}

flow/designs/nangate45/bp_fe_top/rules-base.json

@@ -99,4 +99,4 @@
         "value": 247483,
         "compare": "<="
     }
-}
+}

flow/designs/nangate45/bp_multi_top/rules-base.json

@@ -99,4 +99,4 @@
         "value": 587157,
         "compare": "<="
     }
-}
+}

flow/designs/nangate45/mempool_group/rules-base.json

@@ -1,18 +1,18 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 271098.37,
+        "value": 424000.0,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 2,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 295108,
+        "value": 451188,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 163160,
+        "value": 198708,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -10300.0,
+        "value": -11900.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -11100.0,
+        "value": -14200.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 4029078,
+        "value": 5795200,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -96,7 +96,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 303227,
+        "value": 461696,
         "compare": "<="
     }
 }

flow/designs/nangate45/tinyRocket/rules-base.json

@@ -99,4 +99,4 @@
         "value": 62486,
         "compare": "<="
     }
-}
+}

flow/designs/sky130hd/chameleon/rules-base.json

@@ -99,4 +99,4 @@
         "value": 6493440,
         "compare": "<="
     }
-}
+}

flow/scripts/synth_preamble.tcl

@@ -63,6 +63,16 @@ proc read_design_sources { } {
       lappend slang_args -G "$key=$value"
     }
 
+    # Automatically blackbox macros from ADDITIONAL_LIBS so that
+    # any competing Verilog definitions in the source files are
+    # ignored in favor of the liberty view, consistent with the
+    # behavior of the builtin Verilog frontend.
+    if { [env_var_exists_and_non_empty ADDITIONAL_LIBS] } {
+      foreach m [get_liberty_cell_names] {
+        lappend slang_args --blackboxed-module "$m"
+      }
+    }
+
     # Apply module blackboxing based on module names as they appear
     # in the input, that is before any module name mangling done
     # by elaboration and synthesis

flow/scripts/util.tcl

@@ -1,3 +1,8 @@
+# Extract cell names
+proc get_liberty_cell_names { } {
+  return [tee -q -s result.string select -list-mod =A:liberty_cell]
+}
+
 proc log_cmd { cmd args } {
   # log the command, escape arguments with spaces
   set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length