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docs/user/FlowVariables.md

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| <a name="TIELO_CELL_AND_PORT"></a>TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| |
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| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| 0|
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| <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
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| <a name="UNSET_ABC9_BOX_CELLS"></a>UNSET_ABC9_BOX_CELLS| List of cells to unset the abc9_box attribute on| |
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| <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
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| <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
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| <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| |
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- [SYNTH_WRAPPED_MULTIPLIERS](#SYNTH_WRAPPED_MULTIPLIERS)
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- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
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- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
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- [UNSET_ABC9_BOX_CELLS](#UNSET_ABC9_BOX_CELLS)
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- [VERILOG_DEFINES](#VERILOG_DEFINES)
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- [VERILOG_FILES](#VERILOG_FILES)
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- [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS)

flow/designs/asap7/aes-block/rules-base.json

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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -106.0,
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"value": -78.0,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
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"value": -5150,
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"value": -2890.0,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
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"value": -52.3,
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"compare": ">="
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},
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"cts__timing__hold__tns": {
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"value": -5670.0,
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"compare": ">="
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},
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"globalroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
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"value": -77.7,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -3020.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
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"value": -25.9,
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},
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"globalroute__timing__hold__tns": {
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"value": -1080.0,
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"compare": "<="
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"finish__timing__setup__ws": {
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"finish__timing__setup__tns": {
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"compare": ">="
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"finish__design__instance__area": {
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}
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flow/designs/asap7/gcd/asap7_gcd_tune.yaml

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samples: 10
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timeout: 1.0
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search_space:
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file: autotuner_new.json
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file: designs/gcd/autotuner_new.json

flow/designs/asap7/ibex/asap7_ibex_tune.yaml

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ray_outputs_dir: /work
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orfs_outputs_dir: /work
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search_space:
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file: /work/configs/asap7/ibex/autotuner_new.json
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file: designs/asap7/ibex/autotuner_new.json

flow/designs/asap7/riscv32i-mock-sram/rules-base.json

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{
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"synth__design__instance__area__stdcell": {
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"value": 1570.0,
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},
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"constraints__clocks__count": {
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"globalroute__timing__setup__tns": {
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"detailedroute__route__wirelength": {
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flow/designs/gf12/bp_single/rules-base.json

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"globalroute__antenna_diodes_count": {
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flow/designs/nangate45/jpeg/rules-base.json

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flow/designs/nangate45/mempool_group/config.mk

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export SYNTH_HDL_FRONTEND = slang
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export LEC_CHECK = 0

flow/designs/nangate45/mempool_group/rules-base.json

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flow/designs/nangate45/swerv_wrapper/rules-base.json

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