fix: correct inverted read MUX in dmem

The sel_mem case arms were reversed, causing every memory
read to return data from the wrong SRAM bank.

Signed-off-by: Ashnaa Seth <ashnaaseth2325@gmail.com>
Signed-off-by: ashnaaseth2325-oss <ashnaaseth2325@gmail.com>

Author: ashnaaseth2325-oss

flow/designs/src/riscv32i/dmem.v

@@ -59,10 +59,10 @@ module dmem (clk, r_w, mem_addr, mem_data, mem_out);
 
    always @* begin
       case (sel_mem)
-	2'b00: mem_out = inter_dmem3;
-	2'b01: mem_out = inter_dmem2;
-	2'b10: mem_out = inter_dmem1;
-	2'b11: mem_out = inter_dmem0;
+	2'b11: mem_out = inter_dmem3;
+	2'b10: mem_out = inter_dmem2;
+	2'b01: mem_out = inter_dmem1;
+	2'b00: mem_out = inter_dmem0;
       endcase // case (sel_mem)
    end